(1) Field of the Invention
The present invention relates to a row decoder circuit for a non-volatile memory device, such as an EEPROM, in which data can be rewritten electrically, and particularly to a row decoder circuit for a non-volatile memory device, such as an EEPROM, in which each cell includes a selecting transistor and a sensing transistor, and in which the rewriting of data is possible for each row constituting each page.
(2) Description of the Prior Art Feb. 23, 1984, at pages 852-858
In 1984, SEEQ company published an article in ISSCC about a decoder circuit for a non-volatile memory device in which the rewriting of data is possible in the form of electrically writing and erasing the data in byte units.
As shown in FIG. 6, of the present application this row decoder circuit includes: a row decoder section 1 for selecting a row line, i.e., a word line WL.sub.1 by decoding a row selecting signal A.sub.X, a column decoder section 2 for selecting a column line Y.sub.1 by decoding a column selecting signal A.sub.X ; a sense line bias section 3 for supplying a bias voltage to a sense line; a row high-voltage supplying section 4 for supplying a high voltage to the selected word line WL.sub.1 ; a column path gate section 5 for passing the column line signals; a column high-voltage supplying section 6 for supplying the high-voltage to the column line; a bit high voltage supplying section 7 for supplying the high voltage to a bit line BL.sub.1 ; and a cell array.
In this conventional row decoder circuit constituted as described above, the erasing of data is carried out in units of byte or row. When a data is to be erased, a high-voltage Vmult is supplied so that the selected word line WL.sub.1, and the column line Y.sub.1 is kept at the high-voltage Vmult which amounts to about 17V. At the same time, the high-voltage Vmult is supplied to a program line PL.sub.1, so that a transistor M.sub.1 is turned on, and at the same time, the high voltage is supplied to the gate of a cell CM.sub.1.
Under this condition, the voltage of the bit line BL.sub.1 is kept at 0 (zero) V, and this zero voltage is supplied through a transistor M.sub.2 to the drain of the cell CM.sub.1. Further, the high-voltage Vmult of the program line PL.sub.1 is supplied through the transistor M.sub.1 to a sense line SL.sub.1 which is a top gate of the cell CL.sub.1. Consequently, electrons are tunnelled from the drain region of the cell CM.sub.1 to a floating gate of the cell CM.sub.1 for the data to be erased, while the threshold voltage of the cell CM.sub.1 is shifted to about 2-5V.
The circuit of FIG. 6 illustrates only one cell as an example. Therefore, in a memory device having 8 input and output terminals, 8 cells are connected to an independent bit line, and a word line is commonly connected to all of the cells. Further, each byte consisting of 8 cells is provided with a byte selecting transistor, and one sense line is commonly connected to 8 cells. Further, one column decoder section 2 is provided for every 8 bit lines, and each cell is allowed to keep independent data through the column path gate section 5.
When programming, that is, when writing data, the selected word line WL.sub.1 and the selected column line Y.sub.1 are kept at the high-voltage vmult, and the program line PL.sub.1 is grounded, so that the sense line SL.sub.1 is connected through the transistor M.sub.1 to the program line PL.sub.1. Further, a bit line BL.sub.2 is kept at the high-voltage Vmult, so that a high voltage is supplied to the drain of the cell CM.sub.1. Consequently, electrons are tunnelled from the floating gate of the cell CM.sub.1 to the diffusing region of the drain, thereby writing the data. Under this condition, the threshold voltage of the program cells CM.sub.1 is kept at -3 to -5V.
Thus, the data of the cells CM.sub.1, which are erased and programmed in the manner described above, can be read by detecting the current flowing through the cell CM.sub.1, after a reference voltage V.sub.REF is supplied through the sense line bias section 3 and the column gate section 5 to the selected sense line, and after a power source V.sub.CC is supplied to the selected word line WL.sub.1.
However, in the conventional row decoder circuit constituted and operated as described above, each byte requires a byte selecting transistor, so that the size of a chip on which the circuitry is located is enlarged. Further, each time data is programmed or erased, the high-voltage Vmult is supplied to the word line, with the result that the gate oxide layer of the selecting transistor connected to the word line is damaged as the rewriting is repeated, thereby shortening the life expectancy (the duration of the rewriting capability) of the non-volatile memory device.